February 2021. I am currently building a little 8bit computer from scratch, based on a W65C02 CPU. Mainly as a new clock generator for the CBM 8032 AV project, which can be integrated with the sequencer computer in such a way that programmed tempo changes or swing will become possible. But it will also have all the audio capabilities of the 8032 machines including our own 8 bit DACs and filters. It will be possible to develop and run new sound routines for CBM 8032 AV project on it, using current technology and not 40 year old parts that might fail any day, and with a vastly improved method of data transfer between the computer and my macbook. Firebird might be used for a variety of things. There is a lot one can imagine doing with a small ( 18cm x 6.5cm x 28cm ) and very robust industrial computer with parallel I/O and audio capabilities: It could control installations, it could become a drum sequencer for Eurorack, it could control camera shutters, it could create ASCII art, or it will make the best tea timer in the world. We will see...

21-02-04 first draft and tests of firmware using the CBM 8032 almost done: bootloader, display, initialisation of the VIA, ACIA, etc... front panel ordered at Schaeffer. Front panel printboard ordered. All parts for CPU board and power supply board ordered. Start to work on layout for CPU board.

21-02-19 I guess I am going to test the complete system on the breadboard. Yesterday first successful run of a program. It now can write its name. Cute.

21-02-21 Struggling with bus timing and/or signal level issues. Western Design Center W65C02S <-> W65C22N do not like each other, cannot write too registers in the VIA. Ordered a W65C22S instead, that should work according to data sheet. Observing two oddities: write or read to an address in the 03xx range, both during reset cycle and in normal operation and issues with sending characters to the display. Seems that write is still low, when address is already gone. Not good. Consider using a more sophisticated clock circuit, that slices ΓΈ2 into two segments, allowing to have a write signal ending way before there is a chance that address or data or CS lines change.